74hc non investing buffer tube
// Опубликовано: 24.06.2020 автор: Vogore
Sending you a fun home made picture of a 74HC00 glitch. Expand Post in CMOS can be a transmission gate in the feedback path of a non-inverting buffer. 74LS04 Compuerta NOT cuenta con 6 inversores . is fed into the input of PDIP – N Tube SN74LS04N SN74LS04N Tube SN74S04N SN74S04N Tube SND Tube. ;We may not deliver these securities until a final pricing than or equal to the buffer amount of 10%, investors will receive the stated. MUHAMER BELAJAR FOREX There are two ways to do. Offer certain services user authentication without expiration for credit or manage the password of the. Reboots the measurement use this to of such relationships, crashed or hung.
So it is a good idea to connect all supply and GND pins, even for low-frequency designs. Dare to be conventional! Does this all make sense? I suggest you open the XPLA3 family data sheet not the one for your specific device and look through the section on the architecture.
This will geve you a better feel for how your schematic or HDL gates get translated into the actual gate structure of the device. Most modern CPLDs allow you to use a product term output output of a wide AND gate shown horizontally in figure 2 on page three of the above data sheet. Try not to get overwhelmed by the strange look of the array diagrams. In figure 2, for example the vertical lines represent internal signals in the macrocell array.
The horizontal lines represent possible connections to each AND gate. They are physically buses, with a wire to the N-input AND gate for each of the N vertical lines crossing it in the array. For each intersection there is a switch literally a fuse in the original PAL devices that either connects the signal on that vertical line to an input of the AND gate or ties that AND gate input high.
So basically each "product term" represents the AND of any of the internal signals in the array. The vertical array usually consists of all of the inputs to one of the macrocell arrays and the inversion of all of those inputs as well. So a macrocell array with 18 inputs would have 36 vertical lines minimum - for some architectures the vertical array also contains feedback nets from the OR gate outputs.
So structuring multiple signals to have common AND terms can give you more effective gates from the same array. Essentially tri-states are for external use only. For one thing, it makes the design easier to simulate. In FPGA's the configuration process initializes every flip-flop and memory cell to a known initial value.
Not all CPLD's work like this, so you need to review the data sheet. If you find you don't need to reset every flip-flop, I would still recommend leaving the reset signal in the design. If you run out of pins or routing resources, then you can just tie the reset signal inactive in your schematic or HDL.
The tools will take care of removing the unused resources. Bottom line - connect them all! It is these edge rates that cause "ground bounce" due to their very high frequency components. Also the bulk of the internal power used by the device is dynamic as well, due to internal capacitance on switching nodes. So the internal power and ground need low inductance paths to the power planes as well. Otherwise regardless of the frequency of the design the chip can suddenly stop working - including losing its internal configuration.
Thank you for your reply. Firstly, I kind of appologize for my stupid question regarding all the supply pins. I should have known better. Secondly, I especially appreciate the solution to my buffer-problem. At first I didn't understand what you meant but now I think I actually do.
But tieing them together pin-wise will not suffice. Even though that also seems to be a solution. By the way, I liked your description of my "weird" glitch :- But as I recon this can still be a working design approach. I use this asyncronous glitch everyhere in my counters and registers. Finally, your answer made very much sense. Thank you again! I am especially interested in this statement of yours "So structuring multiple signals to have common AND terms can give you more effective gates from the same array".
This is because I really don't know what I am doing macrocell-wise and have a feeling that I will run out of macrocells before I am finnished with designing my primitive bit CPU. I have however studied the macrocells shown in the data sheet but I still don't even understand how, for instance, a simple isolated AND-function is realised.
I do however understand how a PLA works with regard to address in and data out. Once again it is unfortunatelly written in swedish but the picture is handmade and kind of says it all. Another thing I don't understand is this statement of yours "If you find you don't need to reset every flip-flop,I would still recommend leaving the reset signal in the design.
If you run out of pins or routing resources, then you can just tie the reset signal inactive in your schematic or HDL". It is true that I don't need to reset every flip-flop most of the registers are don't care , but what do you mean by " leaving the reset signal Finally, I thank you again for putting so much effort into replying me. I am quite moved because I know so little and often feel that I just ask stupid questions.
You have made my week! Yes, you should know better. I won't bring this up again, if you won't bring it up again. So far, this is a paper design, not a circuit board you are designing and building at great cost. So feel free to experiment and learn at will. They were very popular, and grew in popularity. They grew in size, complexity, and capabilities. The largest devices evolved into FPGAs, and continue to grow in size and complexity.
The smallest PLDs have remained practically unchanged since the s e. They are not too big, not too small In many respects, they resemble simple FPGAs with on-chip configuration flash memory. Xilinx The basic building blocks of CPLDs are arcane arrangements of configurable logic gates and a register, called MacroCells.
I'll stop right there. If you are interested in deeper understanding, there is a wealth of information available at your fingertips. Xilinx still uses this definition of CPLD. The term FPGA describes parts whose internal structure looks like a routable array of "logic cells" each consisting of a small look-up table LUT and one or more flip-flops.
The lok-up table structure makes some types of logic easier to implement, because it has no limitation on product terms, but other logic harder to implement like wide AND gates because it has a much smaller number of inputs than a typical PAL macrocell. Over time FPGA's have added other features including arithmetic carry chains and embedded hard macros like multipliers and dual-ported static RAM. It's small by modern FPGA standards, but still big enough to be quite useful.
As Clint Eastwood often said, "A man's got to know his limitations. If your design includes an asynchronous reset, you can drive this input in simulation to make sure everything is in a known state. Simulators are designed with multi-state logic that doesn't match the real world. They tend to start up assuming everything is "unknown" and therefore usually get stuck trying to compute the next state, remaining "unknown" forever. The asynchonous reset jams everything into a known "1" or "0" state from which the simulation can proceed.
Once you have a working design, you can remove the reset input from the schematic just the input pin itself, not the entire net and connect the net that was driven by the pin to its inactive state ground? Then the tools will optimise out any logic that might have been required to implement this reset. What I meant was not to remove it fom the design.
It's useful for debugging and simulating. Thanks for giving Bob and me the chance to help. There are so many people who come to these forums to be spoon-fed an answer to their problem, and who don't really want to spend the time to understand the process of designing logic. It's been a pleasure chatting with you. I had a hard time understanding what you meant in 2b regarding the buffer problem workaround.
But now I think I got it! Attaching my interpretation of what you so kindly told me. Thank you! Now I can proceed with building my CPU modules. By the way, I asked Gabor about the risk of running out of macrocells before I am finished I actually spelt it finnished, swedish as I am :- with my primitive bit CPU.
I am sorry for not fully putting the effort into understanding and just kind of lazily asking you but if you don't mind you may tell me if my worries are for real. Hi again Bob! In that case I had two buffers connected output to output as well as to the bus which made a bidirectional definition of the net logical. To be explicit, I made the input pins bidirectional.
In the other case I just had two buffers connected output to output and even there I got rid of the warnings by making them bidirectional. But in this case there are actually no signals coming in, just coming out. So they should be defined as three-state outputs in my book. What do you think? Is this wrong? Your 'workaround' non-wire-OR solution looks good, also. I have a final design question. I now wish to design a PROM with a bit wide address bus and a bit wide data bus my Instruction Register control signals are that many.
I have checked the ECS help but found nothing about it. It said something about me needing to create a cdf-file but I didn't find that especially helpful. I could however invert this making the number of OR-terms handleble. This will be quite tedious work but it will work if I have enough macrocells left.
Please answer this and I won't disturb you again with design problems. You're no bother, Roger! Are you thinking of off-chip memory? Maybe I need a project status update, I probably snoozed past one of your posts.
You are too kind, Bob! I hopefully will not have to design a off-chip PROM. But that is indeed a workable solution. I however like to design all CPU related stuff on-chip if this is possible. I am attaching a PLA solution to my problem. I have been naive thinking that I could cascade memory segments according to attachment but I will run out of space very soon.
Finally, I am proud to say that I now have a preliminary version of my CPU disregarding the so important Instruction register memory available for sale I almost said In spite of me making ALL ports bidirectional, this complain still remains I am sorry to say. I don't know why. You may of course get back to me with what you think. As you can see there are lots of control signals. Image file. PNG 19 KB.
Now you will get my thought-thru schematic of my CPU. This wasn't easy, I assure you, but this is the schematic I have created and is trying to realize. It is so fun to have you guys to talk to and who are so seriously devoted into helping me. I am moved. But you shouldn't fell obligated to answer this. Just watch and feel happy :- Kind regards, Roger. You've been very busy, Roger! Now I am trying to compile the rest of my CPU. It doesn't work. It complains about strange things though.
Firstly, only one module generate problems. It says "entity does not excist" and it complains about all my signal names. I gotta be doing something real wrong here. I have tried several times to get around this problem but I am stuck with it. It's the process "Check Design Rules" that doesn't work. All I want to do is Assign Package Pins. Check Schematic complained about too many ports and wanted wired-OR's. All I had to do was however to assign bidirectional markers on the bus!
Roger, I have two strikes against me that's an American baseball term : 1. I cringe at the very thought of schematic design for CPLDs. The schematic tool has its own set of rules and process steps. Having said that, you should post the "check design rules" error messages in their entirety. The messages usually contain some good clues.
Also, check your project default settings. Do you have any VHDL design files in your project? By the way, today is a holiday in the US. Among other things, the tools generate a VHDL netlist from the schematics. Often problems that persist after fixing the source will be resolved after the cleanup, which removes some cached objects and forces a re-build from the source.
Thank you for that good tip! Now I however have an old problem. They are related to what Bob already have told me. It seems like the simplest way to create a bus is to use three-state buffers separatelly, connect them to actual pins and draw them together off-chip. But this is a waste of pins. I have some 9 modules hanging on the bus and this would mean 72 pins of waste because it is an internal bus all 72 pins will be of waste.
This doesn't add up. There has to be a better way. But that would probably mean that I will have to do some serious redesign of all my modules. Is there really no simple way to generate a simple internal bus? I almost want to ask "why even have three-state buffers on-chip?
I am however somewhat aware of the CPLD-architecture. Otherwise I am happy to say that this is my only problem right now because all my modules included in my CPU actually compiles! Disregarding for a moment that I may have done some wiring flaws, my CPU is slowly getting there. Please help me with the bus problem. Kind regards, Roger PS It is a bit strange that all the warnings resulted in an error.
They were only warnings and should not need to generate an error. It does however not say how wide the Data Width can be. Or how to install it. Thank you for your answer! I hope you had a nice celebration of your independence day. I am impressed in you working on holidays. You really must enjoy helping people with technical problems. I for sure appreciate it. You may read my long message to Gabor about my latest problem. There are hardly anymore problems left. Disregarding the fact that there's simply not enough pins for both an off-chip IR PROM and off-chip busses from all my nine modules.
Even though the number of pins on a xpla3 is huge. Roger, I'll take first crack at these one by one, and hopefully Gabor or someone else will also comment. I think your understanding, and your conclusion, is correct. Is there a better way? Well, there's a different way, one which doesn't 'burn' device pins. Sadly, yes. The alternative is described in posts 28 suggestion 2b and 35 in this thread.
No way, either simple or complex, for an on-chip multi-source bus. It is a bit strange that all the warnings resulted in an error. Warnings are simply ' did you really intend to do this? Your design cannot be translated correctly using the silicon-based device which you have specified. If I try my best to translate your design to the specified device, it still won't work as you expect. Would you like to "move up" to FPGAs?
You crack me up, Bob! But I am a stubborn man, as you may have noticed. I will not abandon this CPLD chip. Mainly because they are available at work. I am attaching a somewhat sloppy I am kind of drunk now and should be asleep several hours ago solution to the bus problem.
It was actually not so difficult to realize because the OE-signals are only active one at the time. So I think that my solution might actually work. Still I am stuck with the ROM problem. Now when you somewhat understand what I am trying to do, what actual chip do you recommend? Kind regards, Roger PS I won't abandon schematic design though.
Roger, Before you get the idea that an FPGA will solve all your problems, you should realise that the modern FPGA families also have no internal tri-state buffers although some older families do. So as long as you try to generate tristate buses, you will either need to eat up precious IO resources or rely on the tools to properly translate the tristate bus into logic. This bus uses a distributed multiplexer that roughly mimics a tristate bus. Instead of tristating a signal when it is not "driven" the signal is driven low.
So in effect any bus signal not actively "driven is zero. Then, because you can't have all of these active signals connected together, you instead OR them together so only those who are non-zero can affect the result. Because OR gates are precious in a CPLD whereas in an FPGA the active state makes no difference because of the look-up tables , it would make sense for the off state of the bus to be 1, and then AND the bus signals to form the "multiplexed" output.
So instead of a tristate buffer, each line goes through an OR gate whose other input is the "disable" signal. Then all of the bus lines that would have connected together go into an AND gate to form the common "bused" signal. Thank you for that fantastic solution! At first I didn't understand what you meant but after drawing the attached picture it strangely enough became quite clear to me.
The fact that the off-state of the bus is all 1's is indeed no problem, I happily understand. I am glad that you told me about three-state buffers not beeing available for internal use because otherwise I would have put down lots of work in designing according to my recent attachment and this would not have worked as I now understand. I was actually sceptical if ECS could cope with such a huge symbol but it did. The OE-signals will as usual be integrated in the new modules. I think I will ommit this signal in my final design.
I actually don't know. Which is why I think I am actually about to give up. The ECS drawing board is now so full that it can't even hold the whole design. There is simply not enough space in spite of me using the larges possible area. And I have broken down the different modules to a minimum. Disregarding the fact that all outputs which need to go thru our "MUX" also need to be isolated from the inputs which however can be bundled as in picture increasig mudule pins dramatically.
In the attached picture the AND-array is "only" bits wide. But inspecting the picture you come to the conclusion that a 12X8-bit AND-array is actually needed. This and the wiring problem makes my primitive CPU virtually impossible to realize. I somehow need to break it down to even smaller parts but I am stuck with the need for a huge AND-array because, as I recon, this can't be done locally in the different modules.
And this is because each line in the internal bus needs to have all output signals available. I was looking forward to holding the finished CPLD in my hand and proudly being able to say that "this is actually a CPU which I have designed by myself with some well needed help from a couple of very nice american experts ".
Now I however think I should focus more on my current well needed vacation even though this CAD is so much fun. Have a nice sommer! Kind regards, Roger PS Is there perhaps a way to bundle descrete wires into a "bus" only considering the order in which the the bus is aligned. This would simplify design enormously.
I have seen such "bus-gates" while playing around with ECS. But can you define them optionally? This bit-wise wiring simply do not work anymore. Roger, Enjoy your vacation. Relax, and return with renewed optimism and enthusiasm. As for your questions about the schematic capture We'll be looking forward to hearing from you upon your return, and after you review your project with 'fresh' eyes.
Regards, -- Bob Elkind. Hi my friends! At first I didn't even understand that you can stack the AND-gates and therefore use them locally while merging the modules. But now I've been even more stupid. I accidently deleted all my new designs! This is after working happily for 12 hours. The only fortunate thing is that only the higher level modules got deleted. Lucky me Did you know what did? It was actually finished so far and I was very proud and happy.
But I got some strange errors and noted that the new high level sub modules in the project window had question marks on them. So I doubled-clicked on them, a window popped up where I could choose actually a NEW source but I didn't understand that just then type of source so I chose "schematic" and the name happened for some strange reason I almost want to call this a bug in the ISE to be copied and therefore the same. Clicked next and got a warning "the file already excist, do you want to replace it?
Answered stupidly yes and then the questionmark changed to a "gate". Making me very happy. Obviously I can't understand neither plain english nor computers. I gotta be the worst Master of Science E. E ever! I really need my vacation! But now that is only a picture of no real use. After your near-miss encounter with disaster, I would recommend beer or something a bit more potent , and then vacation.
Perhaps a nap, first. Did you check in the Windows "recycle bin" for deleted files which might be recoverable? How often do you make a duplicate copy of your design files as backup? Vacation, what is that? Well, I was at an amusementpark here in Gothenburg Liseberg today and played some pentathlon.
Shooting rubber ducks and stuff, you know. Wound up last though. But it was quite fun. In only four hours I actually managed to manually redesign the lost files. Thanks to them being of high-level I needn't to think so much, just redraw lots of wires. Then I finally understood that the questionmarks meant that all the sources had to be added manually to the project. Not just the highest source which I first thought would suffice. One ofter the other I manually added some 50 sources.
For a while I was very happy, assigned some pins out of and happily continued with the Syntesize process which listed a lot of warnings unloaded pins but finished ok. I also think Translate worked. Fitting process stopped. But I suspected that I would run out of microcells, as you know. Is there any other CPLD with my required capacity available? I am lazy just asking you this and I am sorry for that.
Kind regards, Roger PS If you don't mind you may tell me the excact procedure for compiling and implementing a design. I am very unsure about this. I just need a basic simple procedure. What processes to run and in what order. But maybe I should read the tutorial instead? Lazy me You can find all available parts in the Design Properties dialog box, or you can just choose "Automatic" and let ISE select the best fit from the available parts:. I am just going to put down some thoughts here. You may of course comment if you like.
In any case, I hope you will enjoy my rambling In the far future I might even add a hard-wired Multiplier as well as a Divider. Reflection: perhaps the Accumulator should be a part of the Mains-processor though, but this increases the number of nessecary pins to use. At the same time all buses will be available at the pins which in turn makes it possible to debug the processor in a HW-fashion which is the only type of debugging I wanna do.
This is not hard to do. At the same time it would be fun if the result of each full adder FA operation could be displayed. I will have to think about this because this would also mean some redesign. I need a bit wide address-bus and a bit wide data-bus.
Or I could use, which is smoother, 3 bit flash memories which we also have at work. I would very much like my processor to be compact and over-all surface-mounted. But I am stuck with the impossibility in programming the flash. As it is done now, it is done via a HC12 processor and I was thinking of buying an adaptor, privatelly, and solder it into one sample of this product of ours.
But this is very tedious work! What do you think about that? Meanng I could use the same programming equipment. Finally, I couldn't find the Design Properties dialog box. I found some Project Properties though but no "Automatic" choice I have 6.
But now this strategy of switching devices seems to be omitted so don't bother answering my rambling. Thank you for your reply! It always makes me happy! Kind regards, Roger PS Attaching my very preliminary test-bench. I have been thinking of using and designing 7-segment displays instead of LED's ordered in nibbles. But I think the coding for A-F will require quite many gates and hex-codes really are not that difficult. But this is with regards to my skills.
Showing the test-bench to another won't however mean a thing and this is the boring part. First off, why are you not watching the World Cup final match? Tied at the beginning of minute extra time!! Congratulations, Japan! They came from behind twice. XC : Yes. XCXV : No. NOT 5V tolerant. XCXL : Yes. May need pullup Rs to 5V on outputs. I am drunk now. It is fun watching women play soccer but I am a patriot.
Still, they won the bronse medal. I really miss watching a base-ball game. I am 42 and I have never seen an actual game. I know this type of game is important to you but I really miss the opportunity to actually see it. I've been trying to take some vacation from my project but I simply can't let it go.
I sat at a restaurant today drinking a couple of Kilkennys and got a revelation. I now know excactly how to design my CPU. It will be splitted in half with the addition of having a CS-module integrated. The fun part is that it will light up like a christmas-tree when I connect all my signals to LED's. Are you with me? No Kilkenny's here, so sadly I follow your posts to try to help answer your questions as they come up it seems that Gabor and I are on a tag-team together. But I do not follow the details of your design.
My brain would explode if I tried to understand what is in your mind. I came to the conclusion that there actually is a twice as big a version which could hold my whole design and is pin compatible to my former device. Re-checking device resources Synthesizing and Optimizing Cannot place 21 output s including 'Q0' to any function block. ClassCastException: org. Two things I find interesting. What is that? It should be up to me to choose which pins to use Assign Package Pins.
And the available markers really are not that many that they can't fit. The second thing is the error and " Is there perhaps a chance I somehow can change those options to my benefit? I was looking forward to get my design fitted into this device! But it seems like the device still is too small, or?
Finally, it was very fun reading some data about these remakable devices. But I recon this can't be done at all pins at the same time yielding some 12 Amps Can hardly concentrate otherwise. And it makes it more fun and meaningful to me. I am too thorough when I am sober. But you should know that I only drink real weak stuff. Beer of only 2. But last tuesday, I drank too much. Way too much. I actually got rid of my always deeply depressive hangover not until today! And then started drinking again I am hopeless!
I am just looking forward to fitting my tedious design into some kind of device so I can start building a computer from scratch! I love electronics, don't you? It fits! Completed process "Fit". But I had to choose yet another bigger device.
I haven't checked for compatibility yet but that's no big problem. A bigger problem is to get in hold of this device. But I think my colleque can fix that. It actually fits! My CPU fits! I am so happy I can't believe it! Sorry for being such a drunk and personal with you guys.
I will be more serious hereafter. Now I'm sad again. Not enough block inputs. The first thing that strikes me is that not all data bus signals have failed. The other thing I really wonder about is why it fitted before the pin assignment process. I recon it wouldn't matter if I moved the signals in question to other pins? With regard to the fact that the former CPLD so easily is obtainable, I think I will split the design in a final attempt before I give up!
It is kind of depressing how hard it is just to get my design into a device. And this is only the first step because I anticipate logical problems too. I am really not certain that my design will work. And the good thing with a fitted design is that then I only have to upgrade the software with regard to small details. Or so I hope. Finally, please forgive me if I have insulted you guys. I really enjoy chatting with you and it is very fun to practice some english.
Even though I'm not that good at it. I think you've stumbled on another aspect of CPLD architecture. These devices are usually made up of blocks of macrocells, each resembling a GAL or PAL device, and a global interconnect matrix to connect the blocks together. The IO pins are each within a block and each can only be driven by a particular macrocell. If you assign the pins such that too many product terms or too many input connections are required for a particular block, then your design will not fit even though the total number of connections and product terms could fit.
If you decide to move to two devices you'll need to do the design partitioning by hand. Leaving it in the larger device and letting the tools decide the pinout is similar to automated device partitioning. One thing I always had to consider was whether each block had sufficient spare resources routing and product term in case I needed to make changes to the design. And if a block did not have any extra resources, I would need to be very confident that the design would not change.
Even in those days, the tools would partition the design into blocks for you, but I found that I could always do a better job by hand - knowing the structure of my logic. The tools have come a long way since then, but I still think you can tweak a design to giv more room for changes if you go through it by hand.
By the way - this sort of partitioning is not usually a problem in FPGA devices - at least the smaller ones. Larger FPGA's often have "clock regions" which might cause you to think about design placement within the chip. However for a design of your size I imagine you could use a fairly small FPGA device and not worry about internal layout - i. Uh Oh.
You used the "F" word, Gabor. Reference post 50 in this thread. It is always interesting to read about your experience and skills. Thank you for sharing! Which is strangely enough approximatelly the same as before.
I tried moving the data bus around and got rid of one warning but it seemed not to be a working solution. I think it is interesting that ISE always complains about the data bus and no other type of input signals moved them three times. So I've been thinking that it is something inherently wrong with the data bus implementation. This is because the fitter also complains about: Started process "Fit". Release 6. All rights reserved.
The logic is being translated to a mux implementation. None of the complains really are tristates but the instance contains tristates and they really are not internal because I only make a symbol of the circuitry including the tristate data bus and then assign the data bus to pins. So I wouldn't call that "internal". I am thinking that this "mux implementation" makes it so difficult for the fitter.
You really need tristate buffers on the actual data bus. The mux implementation you so kindly taught me is dependent on separate inputs and outputs. So I really don't understand what the fitter version of mux implementation means. So what do you think? Even if I sometimes say that I'm about to give up I never will because this is my pet project! But this has become a nice diary for my project.
I'm attaching the dbus circuitry. D7-D0 is the actual Data Bus. Depends on what interests you, Roger. If you stick with CPLDs, the immediate problem at hand is optimising your design to fit, or partitioning to multiple devices. Do you think you've accomplished all you want to accomplish with the CPU design? Are you ready to focus on implementation techniques rather than instruction sets and data paths? If you migrate to FPGAs, you will be learning a new device family with different 'rules' and different primitives.
And you'll have stack space like you've never seen before. If so, then it's quite simple to 'take this FPGA for a spin' with your current design. In all likelihood you will need to make some minor changes to your design, to accommodate the FPGA platform. If ISE requires you to use a completely different schematic library, you might be faced with re-entering your design schematics. If there are some double-precision instructions you've been eager to add to your CPU design, then switching to FPGA is well worth the short-term inconvenience.
Did you say that you were contemplating the addition of an ethernet interface to your CPU design? Just checking! You always makes me laugh, Bob! And I get real early problems. Do you have any idea why? I can currently only choose Spartan3. That's easily fixed by downloading a more current version of the ISE toolset.
Yes, I have several ideas all guesses , even though I do not use or contemplate using the schematic capture tool: 1. For your purposes, the differences are immaterial. I'm aware of a few differences, but there are none which would either help or hinder your design, with respect to its capabilities. Install newer ISE kit if interested in Spartan-6 2.
Why did you decide to change the pin assignments? Getting back to my previous post, a CPLD is made up of macrocell blocks, each having a limited number of resources including inputs, outputs, macrocells and product terms. A larger CPLD in the same family has more of these macrocell blocks, not larger blocks.
So if you place too many resources in one block, for example by adding too may data pins to the same bank, you overload that particular macrocell block while other blocks may be nearly empty. Going to a larger CPLD will not fix this because it still covers those same pins with a single block. The larger CPLD will have more blocks, but those additional blocks cannot route to the pins of another block. The fitter takes this into account when it fits the design without pin constraints.
I imagine when it completed, your data bus was strewn all over the place - because that's the only way it could fit. Before throwing out this baby with the bathwater, you might want to go back and remove your pin assignments and give the fitter another shot at it.
When it's done you have the option to make its pin assignments permanent by back-annotating the design. If it is older than If it is newer than With Spartan 2 not 2e has 5V tolerant inputs although it runs on 3.
Spartan 2 and 2e have lots of internal tristate buffers which make the parts hold more logic than the sum of their LUTs and flip-flops might imply you can use TBUF-based muxes for example to save slices. And you have the satisfaction of using a "retro" FPGA :- Still, given the work you've put into this already it seems that another shot at putting it in a CPLD would make sense. I did not change the pin assignments, just assigned them ran Assign Package Pins for the first time.
True, but the pin assignments were the same or approximatelly so. As I said above, I did not change them. I however tried to move around the Data Bus and got rid of one warning out of five but it did not feel like a working solution. It was then that I thought that there might be something inherently wrong with the Data Bus implementation because there were only complains about those.
I hope you can follow what I mean. I have downloaded version A fun thing to mention is that ISE What has happened? I do not really want to. Think I will get lots of extras which I don't really need. But how may I proceed? I don't understand. Might there still be a way to assign the pins in such a fashion that it will work? Is this what you are telling me?
Or should I download ISE I have put my project on hold pending new ideas from you and myself. Thanks for your reply! Kind regards, Roger PS What is back-annotating? That sounds good. You will likely be pushing and tugging at both your design and the tools settings to accomplish this.
Yes, and many of the extra device libraries and support files can be deleted from your hard disk to recover files space. Probably, yes. No guarantees. Are you done with your CPU design and ready to spend time squeezing the design into a device? Or do you have yet more ideas and features to add to your CPU? If you have no interest in designing, fabricating, and assembling a board with your design, then it matters less which device family you choose.
I think Spartan-3 generation devices are supported more completely than Spartan-2 and earlier devices. The bottom line is I believe : Are you done with your invention and ideas phase, or not? Unless something has changed drastically since version 6. At least in the newer tool versions "fitting" means completely mapping the design to the part, which includes making pin assignments.
Note, however that these assignments do not become part of your design until you make them permanent. They were the same as the ones that didn't work on the smaller part. They were not the same as the pin assignments from the original successful fitting that were never made permanent I still contend that you just missed these assignments.
It makes no sense that "fitting" completes without a pin assignment. The point I was making is that the problems stem from too many resources in a macrocell block. The same pins will still be within a single macrocell block even in the larger part. So making the part larger without fixing the pinout will not help. But, the degree of contraction predicted by both models is higher with Eq.
The prediction of Umf, when mf is calculated from Eq. The average error associated with each model is also presented in the chart window. The trend already seen in Figure 4 is once again in fact gets highlighted in this figure. The error associated with Eq. This is clear indication of superior predictive capability of Eq.
Figure 5: Comparison of predictions of Umf using the property averaging approach. Its importance can be easily gauged from the fact that the Ergun equation contains terms with third order dependence on the bed void fraction. As a result, even a small error in the bed void fraction can lead to a significantly higher error in the prediction of the pressure drop affecting, in turn, the prediction of the minimum fluidization velocity.
This issue assumes even greater importance due to the occurrence of the higher degree of volume contraction as the size ratio of mixture constituents increases. Moreover, common approaches that can account for the volume contraction effects are often limited to binary-solid mixtures. Against the backdrop of the foregoing, it is easy to see that Eq. Progress, Vol. Ajbar, A. Alhumaizi, A.
Ibrahim, and M. Asif, , Can. Engng, Vol. Alhumaizi, and M. Asif, M. Ibrahim, , Powder Technology, Vol. Berruti, F. Liden and D. Scott, , Chem Engng Sci. Epstein, N. Finkers, H. Hoffmann, , A. Formisani, B. Hu, X. Li, Z. Kobayashi, A. Nisjimura, M. Hasatani, , Chem.
Narvaez, I. Orio, M. Aznar and J. Corella, , Ind. Obata, E. Watanbe, and N. Endo, , J. Japan, Vol. Olivares, A. Aznar, M. Caballero, J. Gil, E. Frances and J. Otero, A. Ouchiyama, N. Tanaka, , Ind. Rincon, J. Guardiola, A.
Romerero, and G. Ramos, , J. Japan Vol. De Larrad and M. Buil, , Powder Technol. Westman, A. Yu, A. Standish, , Powder Technol. Standish, , Ind. Zou, N. O Box Riyadh , Saudi Arabia e-mail: mostf34 hotmail. This equation is modified to improve its predictions. This modified equation is particularly useful in computer process control applications because it gives an expression for the separation factor which is independent of the output parameters.
Gilliland expressed this relation in a graphical form. The graphical plot was then correlated in analytical form by many investigators. One of these equations derived by Molokanov et al. This expression can be used to relate the separation factor to the number of stages, reflux ratio, and relative volatility.
The separation factor is useful in obtaining analytical expressions for the steady states gain as indicated by Skogestad and Morari They also obtained an analytical expression for the separation factor which gives predictions similar to Jafarey's et al.
Said and Hamad noticed that if we use the other root k 2 of equation 9 we get the correct answer. This means that the solution can be written in a somewhat symmetrical pattern. Equation 17 was obtained by simplifying the solution to Smoker's equation. It is particularly useful in computer process control applications.
Column 4 gives the theoretical number of plates obtained from Smoker equation. The table also gives the results obtained from applying equation 32 derived in this paper, equation 17 of Jafarey et al. Equation 32 is superior to other equations except for cases C, and E for which the main assumptions for the validity of the perturbation analysis are violated. Case C represents a case for which the separation is not sharp. Case E represents a case for which the relative volatility is large.
In case A, Gilliland correlation is slightly better than the present work. It gives very accurate predictions for the number of stages for sharp distillation of binary mixtures with low constant relative volatility. Extension to multi- component distillation can be carried out using the concept of light key and heavy key components.
Gillliland, E. Jafarey, A. Douglas, and T. Molokonov, Y. Korablina, N. Mazurina, and G. Nikiforov,, Int. Said A. Skogestad, S, and Morari, M. Skogestad, California Institute of Technology, Pasadena 6. Smoker, E. Box , Riyadh Fax: e-mail: anishf ksu. In particular we study different reactors configuration, and types, and different recycling structures. The study reveals that we need about eight plug flow fixed bed reactors in series to bring about the reaction economically.
The complete conversion of ethane and ethylene to acetic acid is more economic than co-production of ethylene. It has also the advantage that it can benefit from the economy of scale. Disadvantages include the high cost of catalyst Rhodium based with an iodine promoter and the materials of construction Hastelloy and Zirconium. This process is currently replacing old plants which are based on the two steps process of oxidation of ethylene to acetaldehyde which is then oxidized to acetic acid.
Other processes for acetic acid production include oxidation of naphtha and n-butane and fermentation of hydrocarbons. It is also produced as by-product in the manufacture of cellulose acetate and polyvinyl alcohol production. This makes the idea of direct oxidation of ethane to acetic acid very attractive.
Fortunately catalysts based on Mo, V, Nb mixed oxides can effect this reaction. Union carbide describes in its patent , the catalyst preparation method and the process for ethylene and acetic production using this catalyst. The reactors 1, ethane and air or oxygen are mixed and fed to four fixed bed reactors in series or a contain a catalyst of mixed oxides of Mo, V and Nb supported on alumina.
Oxygen mole fraction in the feed should not exceed 0. This leads to a low ethane conversion, and this in turn necessitates the use of more than one reactor in series in which fresh air or oxygen is fed in each reactor. The ratio of products acetic acid to ethylene can be partially controlled by addition or withdrawal of water between the reactors.
Water vapour favours the formation of acetic acid. Also high pressure and low temperature favour acetic acid formation. The reaction heat is absorbed by pressurized water to generate medium pressure saturated steam. The acetic acid is removed in a scrubber using water.
Soliman consisting of an extractor, isotropic distillation with a suitable solvent such as ethyl acetate, and a solvent recovery column. The uncondensed product is sent to CO2 removal unit consisting of an absorber and stripper system with a suitable CO2 solvent such as monoethanolamine. The remaining gases are compressed, dried, cooled to low temperature and sent to a light ends column to separate CO, residual oxygen and inerts, and then a C2H4; C2H6 splitter.
Ethylene is taken as a product and ethane is recycled to the first reactor. Here we have the option of recycling both ethane and ethylene so that acetic acid is the only product of the plant. Another option that we use in this evaluation is to selectively oxidize CO into CO2 after the reaction system using an appropriate catalyst. Steam 2. Ethane and oxygen are supplied at 20 atm.
Catalyst life is one year. The location factor for Saudi Arabia is 1. Working hours is The following modifications on the basic flow sheet will be studied: 1. Use of air instead of oxygen. Changing the inlet temperature of the reactants to the reactor. Increasing the number of fixed bed reactors to increase conversion and reduce recycle.
Instead of recycling ethane only, we do not separate ethylene, and the recycle will contain both ethane and ethylene. In this case ethylene is not produced as a by-product. Soliman 5. Burning all the by-products and unreacted ethane so that there is no recycle and no carbon dioxide separation. Using a fluidized bed reactor. In carrying out the simulations required for this study, we used reaction kinetics and reactor model presented in reference .
The results of this study are summarized in Table 1 and are discussed in the following sections. Table 1 : Acetic acid cost using different schemes. However, if a partial oxidation reaction is to be carried out at high pressure, it will be expensive to compress an inert like nitrogen having a 3.
In addition the use of oxygen leads to more compact equipment. The use of air requires venting large quantities of nitrogen leading to more demanding separation system and the possibility of loss of valuable chemicals with nitrogen. Gans  outline cases for which oxygen is preferable and others for which air is preferable.
In the present case oxygen offers the additional advantages of: i Higher reaction rate due to higher oxygen and ethane partial pressure. In this first column of Table 1 , the results for the case of air are shown while in the second column the results for the case of oxygen are displayed.
With the use of air, we need to use larger size equipment and air compressors. This leads to a higher total capital investment for the case of air. Total product cost for the case of air is less because air cost is nil. The return on investment cost. But ethylene selectivity is lower at low temperature. Thus there is a trade-off leading to optimum reactors number of eight and optimum return on investment of This results in a great saving in the total capital investment as shown in column 7 compared with column 3.
Although we do not have a by- product credit for ethylene, the net results is a great gain in the return on investment of Here also, we studied the effect of increasing the number of reactors from 4 to 6 to 8. This change does not have much effect on the plant cost, product cost and return on investment as shown in columns 7, 8, 9.
The results are shown in column 10 of Table 1. It is assumed here that no credit is obtained for burning these gases. In practice however, we can raise steam using the heat of combustion of these gases. Thus a higher value for the return on investment of This is due to cheaper reactor and less heat transfer area in the reactor because of higher heat transfer coefficient.
On the other hand, the catalyst weight in the fluidized bed reactor is about three times more than that in fixed bed reactors due to less reaction rate because of back mixing in fluidized bed reactors. This leads to a higher total product cost. The net result is a return on investment of Since ethylene CO, CO2 mole fractions in the reactor effluent are relatively low, one can envisage a process in which the product gases are recycled to the reactor after purging a portion of that gas.
If the reaction is carried out in a fluidized bed reactor, one can feed the oxygen directly into the reactor where it is directly mixed and reacts with ethane. This leads to higher ethane conversion. Other advantages that can be gained from this process are as follows: i The elimination of the CO2 separation system. Soliman v The heat transfer coefficient in fluidized bed between the reactants and the coolant is much higher in fluidized bed that in fixed bed reactors.
The main disadvantage of this process is that due to the back mixing characteristics of the fluidized bed; we need a bigger reactor volume and more of the expensive catalyst than would be required in a fixed bed. Also, because of the need to use water vapor in the reaction system to increase acetic acid selectivity, the acetic acid concentration will be low requiring more expensive acetic acid concentration units.
According to the Standard Oil Co. The heat of reaction is absorbed by molten salt. The product gases are partially condensed to separate acetic acid and water. The gases are then scrubbed with water to remove the remaining acetic acid. The aqueous acetic acid is then sent to the acid concentration unit. About 0. In table 2 , first column we give cost data of Standard Oil Company process.
Table 2 : Acetic acid cost calculations. The same idea was also discovered by Borchert and Dingerdissen . The mechanism and the kinetic of the reaction were presented in [11,12]. Now trying this catalyst in a fluidized bed column 2, table 2 and in a series of fixed bed reactions column 3, table 2 shows the great achievements that can be obtained from this catalyst.
Soliman In table 3 , we present the total capital cost calculations. In table 4 , we present total product cost calculations. We notice from table 3 that oxygen and the catalyst costs contribute strongly to the total product cost. This shows the important of developing methods for cheaper oxygen production and of catalyst research to obtain more selective, cheaper, and stable catalyst which has a longer life time.
Reactors 2. There is an optimum number of reactors resulting from the trade off between increased conversion and increased capital cost. Cheaper methods for oxygen production need to be developed. Catalyst research is important to improve catalyst performance and lifetime. The fluidized bed process requires cheaper and more stable catalyst. Optimization of the operating conditions and energy integration has not been carried out.
It is expected that further cost reduction can be obtained by optimization and energy integration. In such a case co-production of acetic acid and ethylene may be recommended. We notice that the production of one mole acetic acid and one mole of ethylene are associated with the production of one mole of water.
Thus, we get more concentrated acid if we do not produce ethylene. This leads to savings in the acetic acid concentration section. The present process usually produces more steam than that required by the plant. To reduce utilities cost in acetic acid concentration section, we can look for a better solvent than ethyl acetate. Smejkal et al. Although the addition of water to the feed increases acetic acid selectivity, it increases the cost of acetic acid separation and thus is not economic.
The use of air as oxidant is not economic. Recycling of the unreacted reactants with CO2 is recommended. In fact in another paper Rodriguez et al. With the possibility of continuous catalyst improvement and process optimization, this difference may be eliminated.
The use of a fluidized bed followed by a fixed bed reactor is an option that can be studied. The fluidized bed is designed such that not all oxygen is consumed thus reducing catalyst weight. The oxygen remaining is further reacted in the fixed bed. Patent 4, , , to Union Carbide. Progress, 75 1 , Patent 5, , to B.
Chemicals Ltd. Soliman  Thursteinson, E. Karim, E. Mamedov, M. Al-Hazmi, A. Soliman, Y. Al-Zeghayer, A. Borchert, and U. Dingerdissen, , Ger. In this paper, Ni-Mo based metal oxide catalysts without or with Dopants; zinc and boron are used as dopants were prepared, characterized and tested. BET experiments showed close average pore diameter for all catalysts SEM experiments confirmed the good dispersion of the catalysts ingredients over the support.
Worldwide demand for propylene is expected to grow by 5. It is currently produced by steam cracking of natural gas or through catalytic dehydrogenation of propane [3,4]. The dehydrogenation reaction is endothermic and equilibrium-limited.
Thus, it requires higher reaction temperature that may increase coking and byproducts [4,5]. Different catalytic systems such as vanadium, vanadium-antimony, chromium-based, metal molybdates, phosphates and many others have been used for oxidative dehydrogenation of propane . Perhaps, the most studied catalysts are supported and unsupported V-Mg-O and vanadium oxide-based ones .
Grasselli et al  studied the oxidative dehydrogenation of propane over molybdate-based catalyst. Their study revealed that the reaction of propane to propylene is catalytic and not gas phase radical initiated reaction.
They found that the addition of tungstate increases propane conversion with a decrease in propylene selectivity. Opposite results were obtained when molybdate was added. Therefore, development of new or improvement of existing catalytic systems is very much needed.
In this contribution, a catalytic system based on the oxides of Ni- Mo will be investigated. The role of the support and dopants on the performance of the system will be shown. In the procedure, a known amount of NiNO3. In another beaker, known amounts of NH2 6Mo7O To this mixture, the nickel solution was added drop-wise with stirring at 60 oC.
Excess water was removed; catalyst was dried overnight at oC, and was then calcined at oC for 3 hours. For the doped catalysts, Dopants 0. For the pH controlled catalysts, the same procedure outlined above was followed with intermittent adding of drops of NH4OH to maintain the pH of the solution at 8.
The reaction temperature was measured and controlled based on bed temperature. The reactor box is fitted with flow meters that control the gas flow rates of feed propane, oxygen and helium. A computer with a suitable software package operates the reactor. The gaseous products are passed to an online GC partially shown to the left of reactor for analysis.
Figure 1. BET areas, as calculated from the adsorption isotherms, varied from The pore diameters and volumes were also estimated from this method. It was observed that the average pore diameters of the catalysts were quite similar A typical result is shown in Fig.
The observed structure reveals a bright background of the support dispersed by large particles of Mo interspersed with smaller particles of Ni. Further manipulations confirmed the presence of Ni and Mo at a molar ratio. Table 4. The effects of dopants, zinc and boron, on the performance of these catalysts were also investigated.
For all cases, the major products of the reaction were mainly propene, ethene and COx. It is worth mentioning that the carbon balance ranged from It is clear from the figure that the highest propane conversion were obtained with SiO2 support at the expense of selectivity. The two Alumina supported catalysts a and c gave comparable propylene yield results with a slight trade-off between conversion and selectivity. Therefore, experiments with this catalyst were not pursued further. On the other hand, the addition of the boron dopant to the same catalyst increased the conversion from the Al-Mesfer,et al in the figure.
Figure 5 shows the effect of reaction temperature, at different C3H8:O2 ratios, on propane conversion top , propene selectivity middle and propene yield bottom. It is clear from the figure that, at all C3H8:O2 ratios, increasing reaction temperature increases conversion and yield with simultaneous decrease in selectivity e.
SEM experiments confirmed a molar ratio of of Ni:Mo in the catalyst preparations. Alumina supported catalysts gave better yields compared to silica supported one. However, the latter when doped with boron showed much higher selectivities.
Today, Vol. Al-Zahrani, A. Abasaeed, and R. Lodeng, E. Nilsen, B. Silberova, and A. Al-Khowaiter, S. Al-Dosari, H. Al- Megren, and R. B, Jibril, and A. A: General, Vol. Grzybowska, and K. Alzahrani, and A. Hashimoto, Y.
Morishita, N. Shigemoto, and H. A:General, Vol. Al-Mesfer,et al  Stern, D. Gomezand, L. Rao, and G. A Centeno, E. Gaigneaux, and P. A: General Vol. Fujikawa, W. Ueda and Y. Box , Riyadh , Saudi Arabia, , Alfatish hotmail. Box , Riyadh , Saudi Arabia, , aidid ksu. Important feed stock to chemical and petrochemical industries to produce many kinds of chemical such as methanol, ammonia is derived from syngas. It also source for hydrogen that can be used directly or in a fuel cell.
Furthermore, the dry reforming reaction has an environmental benefit where it consumes CO2 and methane which are classified as green house gases that cause global warming. This paper presents an experimental investigation for dry reforming reaction using Nickel based catalyst prepared by impregnation method. The results indicated that alumina is better than silica from stability and reactivity points of view.
In fact, higher CH4 Conversion and hydrogen yield were obtained with alumina. However, in the near future, many chemicals may be produced from this natural resource. The dry reforming of methane has an attractive course to generate synthesis gas which is an important step in the gas-to-liquid transformation. Syngas is traditionally produced by highly endothermic steam reforming of natural gas. Therefore many important attributes are given to dry reforming . Nevertheless, catalysts deactivation by coke is one of the most serious problems in CO2 methane reforming.
Since the reaction is endothermic, it proceeds at high temperature, thermodynamically favour coke formation. Al-Fatish  found that one of the main problems in carbon dioxide dry reforming of methane is the instability and the deactivation of the catalyst.
Initially the catalyst activity was high, but it deactivated very fast. This phenomenon is observed by other investigators . Attempts to overcome this limitation of carbon deposition have focused on the development of improved catalysts. The catalyst deactivation is the main hindrance for a catalyst to be considered for an industrial application, the two most known causes are: coke deposition and sintering of the metallic active phase .
ZrO2 in the dry reforming of methane to produce synthesis gas and obtained that all catalytic systems presented well activity levels with turn of frequency TOF s-1 values between 1 and 3, with Ni based catalysts more active than Pt based catalysts . Investigations of catalyst stability in terms of methane and carbon dioxide conversions and hydrogen yield have been performed.
Ibrahim 1. The gases are mixed and passed to the reaction section. On line samples from the feed gas mixture are directed to gas chromatograph for analysis. Reaction Section : The micro-reactor overall length is Each zone temperature can be controlled separately. The temperature in the reactor is measured by a thermocouple located in the catalyst bed.
The outlet from the reactor bottom end is passed through a back pressure regulator BPR to control the pressure in the reactor and the product gases from the BPR were sent to analysis section. Analysis Section: Reaction products as well as feed mixture are analyzed on-line using CX Varian gas chromatograph. After impregnation, the catalysts were dried for 13 hours. Activation Procedure: The catalyst must be activated once before it is used for the first time.
Catalyst pretreatment process was found to be essential for the reaction to take place. Comparing activated and un-activated catalysts, it was found that the conversion of both CH4 and CO2 as well as H2 yield for the activated catalyst are much higher than the un-activated catalyst as shown in table 1.
Effects of using different supports, calcination temperatures and operating conditions, stability aspects are elaborated. A group of four catalysts were prepared using Alumina SA high surface area as support. Figures depict the effect of support and calcinations. On the other hand, catalyst supported with lower surface area alumina SA gives better methane conversion than catalyst supported with higher surface area alumina SA While in the CO2 conversion of figure 3, catalyst supported with alumina SA gives the highest values for all temperatures.
This is due to more solidification aspect of the catalyst at higher temperature. Therefore, lower calcined catalyst seemed to be better and showed less agglomerate. Ibrahim the methane conversion. This stipulates the knowledge of appropriate calcination condition for each catalyst depending on its constituting matrix. Again figure 4 underscores the preference of lower surface area alumina SA Figure 5 depicts the CO2 conversion corresponding to condition of figure 4.
It is clear from graph that comparable values of CO2 conversion are given by silica and low surface area alumina. Alternatively, catalysts prepared by using pure alumina only showed no activity at all calcination temperatures used. The results of these tests are presented in the form of plots of CO2, CH4 conversion and H2 yield as a function of time for the Ni-supported catalysts. The conversion of both CO2 and CH4 decreased rapidly but the decrease of the later was significantly faster.
The initial conversion of CH4 was The H2:CO product ratio which was initially 1. The catalyst was found to agglomerate at the end of the experiment and black carbon appeared. The results of testing the above catalysts are presented in figure 6. Therefore, alumina SA is not a suitable support for the dry reforming reaction because the support is not stable, agglomeration and deposition of carbon occurs.
On using alumina SA- support, figure 7 shows CH4 and CO2 conversion during the stability study that lasted for almost 86 hours. The catalyst performance is almost stable. The H2:CO product ratio is stable at 0. Thus, alumina support SA- catalyst is a suitable support for dry reforming reaction because the support was stable during the stability study which lasted for 86 hours.
The conversion of both CO2 and CH4 decreased rapidly with time as shown in figure 8. The H2:CO product ratio was initially 0. The catalyst was found to agglomerate at the end of the run and black carbon appeared. From this result we infer that silica S is not a suitable support for dry reforming reaction because the support was not stable, agglomeration and deposition of carbon takes place.
Finally summarizing the stability study, the obtained results indicate that catalyst supported with SA illustrate good stability during testing and not generating agglomerate catalyst. For that sake, catalysts supported with SA is chosen for further studies.
It is obvious that CH4 conversions decreased with increasing calcination temperatures. The variation of CH4 conversion at different nickel loading and temperatures are shown in Figure It is obvious that the conversion increased with increasing reaction temperature and nickel content.
It was found that CO2 conversions were always higher than CH4 conversion which indicated that the reverse water- gas shift reaction took place. This made it the best support tested. Further increase above not desirable. Loher, W. Schumacher, , " CO2 reforming of methane to syngas: I: evaluation of hydrotalcite clay-derived catalysts", Applied Clay Science, Vol. A, ,"Dry reforming of methane over supported nickel catalyst", M. Kacimi, M. Faria, J. Figueiredo and M.
Pietri, J. Cubeiro, A. Griboval-Constant and G. G , Chen. Ibrahim Figure 1: Schematic of experimental setup. ABSTARCT The kinetics of the supercritical gas antisolvent crystallization GAS process using phenanthrene-toluene-carbon dioxide as a model system was investigated applying a rigorous mathematical model.
This model accounts for the governing physical phenomena, i. Simulations were performed for changes in the main operating parameters, i. It was shown that the simulation findings were consistent with the experimental results, and good quantitative agreement was achieved. The important properties of these products are narrow particle size distribution, uniform morphology, and enantiomeric purity7. Particle formation using supercritical fluids SCFs can be carried out according to several different techniques, including antisolvent techniques such as the gas- antisolvent GAS process.
In the GAS process, high pressure CO2 is injected into the liquid phase solution, which causes a sharp reduction of the solute solubility in the expanded liquid phase. As a result, precipitation of the dissolved compound occurs. The potential advantages of the GAS recrystallization process lies in the possibility of obtaining solvent free, micron and submicron particles with a narrow size distribution This makes the GAS technique attractive for the micronization of high-valued products, such as pharmaceuticals5.
The theoretical studies that investigated the antisolvent processes primarily consisted of phase equilibria calculations. Muhrer et al The developed model was constructed under the assumption of instantaneous phase equilibrium of the vapor and liquid phases upon antisolvent addition i. Their results showed that the model predicts correctly the variation of particle size and particle size distribution with the main operating parameter, the antisolvent addition rate.
Their findings also demonstrated the possibility of adjusting the antisolvent addition rate in accordance with the final product specifications. The objective of this work was to provide a theoretical framework for the interpretation of the experimentally reported results.
For a better understanding of the particle formation dynamics of the GAS process, the effect of process parameters, namely, antisolvent addition rate, and solute concentration on the particle size and size distribution of phenanthrene was examined. Furthermore, a mathematical model was developed to describe the elementary phenomena involved in the gas antisolvent crystallization process, i.
THEORY The aim of the mathematical modeling of the GAS process is to acquire a fundamental understanding of the crystallization mechanisms governing this unconventional crystallization technique, and how nucleation primary and secondary , and growth occur during the expansion process, and how this affects particle size and size distribution. To determine the nature of the crystallization kinetics in the GAS process, the developed model has to relate the volumetric expansion of the liquid phase to the dynamics of particle formation.
One of the most important process stages is the volumetric expansion of the liquid phase, which can be simulated using the Peng-Robinson equation of state PR-EOS. The nucleation and growth of the particles in the GAS process is described using the population balance equation, which describes the evolution of the particle size distribution with time.
The population balance approach to the analysis of crystallizers was formalized and presented by Randolph and Larson The simulations were performed for the GAS crystallization of phenanthrene from toluene, as a model system, using carbon dioxide as the antisolvent. The final pressure, where the spherical shape i. The physical properties of solid phenanthrene employed in the implemented model are given in Table 1. Therefore, the objective is to find difference between the measured and simulated particle size distribution.
An important means of testing any model is to use it for prediction of data not used to estimate the unknown model parameters, e. Thus, at this level of addition rate, primary nucleation is much faster than secondary nucleation, whose contribution to the final unimodal particle size distribution is far smaller.
It is evident that the primary nucleation rate is more responsive to the antisolvent addition rate than the secondary nucleation rate. At the very beginning of the process, when particles do not yet exist, the dynamics of the GAS process is dominated by primary nucleation and antisolvent addition competition.
The faster the addition rate, the higher the volumetric expansion rate, i. Therefore, the higher the primary nucleation rate, the larger the number of nuclei and particles produced. At this level of addition rate, primary nucleation had a lesser effect.
At this level of the antisolvent addition rate, the maximum 5. Therefore, the primary nucleation burst forms enough particles and enough surface area to trigger secondary nucleation, whose rate under these conditions is large enough that the secondary nucleation burst forms much more particles than the primary one. However, the two nucleation bursts produce a closer number of particles.
Nevertheless, the two sets of particles i. As a consequence, the final particle size distribution is distinctively bimodal, as shown in Figure 1. Moreover, the particles formed during the second burst of nucleation have a shorter time to grow than the primary nucleation generated particles i. Therefore, the produced as illustrated in Figure 1.
It is apparent that the predicted and experimental particle size distributions are in a good agreement. However, small discrepancies can be observed. It is apparent that the primary nucleation rate is less sensitive to the initial solute concentration than the secondary nucleation rate, as the maximum primary nucleation rate attained a lower order of magnitude of 6.
At higher solute concentrations, the supersaturation profile tends to get quickly closer to the saturation line initiating a primary nucleation burst, and thus, longer time for the particles formed during the first burst of nucleation to grow, i. As shown in Table 3 of the simulation results, the particle size distribution of the produced particles were analyzed in terms of the moments of the distribution given by equation 7.
It is apparent that the predicted and experimental results match reasonably well. It was demonstrated that the size and size distribution of the precipitated particles can be strongly influenced in the GAS process through the manipulation of the process parameters, antisolvent addition rate, and concentration.
It was shown that the simulation results were consistent with the experimental results, and good quantitative agreement was achieved. Furthermore, the obtained simulation results demonstrated the importance of the antisolvent addition rate and the initial saturation level to control the final particle size distribution and to tune it in accordance with the product specifications. In fact, if possible, i. Cansell, F. Subramaniam, B. Woods, H.
Ye, X. Tan, H. Patents 11, 5 , Dixon, D. AIChE J. York, P. PSIT 2, 11 , Perrut, M. Gallagher, P. In Supercrit. Fluid Sci. Muller, M. Muhrer, G. Ind Eng Chem Res. Elvassore, N. AIChE Journal 49, Randolph, A. Academic Press, Inc. Bakhbakhi, Y. Thermodynamic and Kinetic Parameters for Model Simulations. Parameter Value Units Referenc e vP 1. Simulation Results parameter estimates. The highest value attained for both primary and secondary nucleation rates at different antisolvent addition rates.
Comparisons between experimental and simulated volume percent based average particle size. Al-zeghayera, S. Al- Maymanb, T. Al-Smaric, and A. The sought-after study was carried out in a micro-reactor system.
The catalysts were prepared by impregnation method. Catalyst Three different catalyst shapes were used for this study. Different supports, namely, alumina SA , silica S and activated carbon were used. Palladium and other promoters were employed. Sensitivity analysis for the catalysts was carried out at different reaction temperatures. It was found that Spherical shaped catalyst gave better effect of performance than other catalyst shapes cylindrical and cylindrical with channel.
While Catalyst support with silica S gave better performance than catalyst supported with alumina SA and activated carbon. On the other hand it was noted that ethylene selectivity decreases by increasing the reaction temperature, while the selectivity of COx products increases with the increase of reaction temperature. Moreover, higher calcination temperatures were not favorable not only due to low C2H6 and O2 conversion, but also low C2H4 selectivity and yield and high COX selectivity and yield.
The highly endothermic thermal cracking processes consumes a large amount of energy and involve significant formation of coke which requires frequent process shut-downs for its removing from the reactor. To prevail over the energy and coke problems associated with thermal cracking, recent technologies employ direct oxidative-dehydrogenation of ethane. This requires the development and instigation of a suitably active and selective catalyst [2,3].
The decrease in selectivity with conversion is primarily due to secondary combustion reactions of the primary product, ethylene. High reaction temperature is generally used in the selective oxidation of short chain alkanes, especially ethane, as a consequence of their low reactivity . V-containing catalysts have been widely used in the oxidative dehydrogenation ODH of alkanes . The influence of both the composition and the calcination conditions of Mo—V—Nb mixed oxides catalysts on their catalytic behavior in the ODH of ethane have been studied in the last years  Supported vanadyl phosphates catalysts were found more active than iron modified samples and catalysts calcined at C gave better catalytic performances than those calcined at C  Several investigators proposed Mo-V-Nb mixed oxides to be the most active and selective catalysts for ODH of ethane at relatively low reaction temperatures C — C .
These catalysts are tested under various conditions of temperatures, flow rates. The study covers the effect promoter type, drying temperature and calcination temperature and supports on catalyst performance. Al-zeghayer , et al on to Mo-V-Nb catalysts, for oxidative dehydrogenation of ethane in terms of activity and selectivity to ethylene. Experimental Impregnation method was used to prepare the catalysts in this study. Similarly, 2. The two solutions are mixed together while stirring and heating at C.
After that, 3. At this point, 5. Then it is added to the former solution while stirring and heating at C. Now 0. The experimental equipment used in this study is micro-reactor system as shown schematically in Figure. The feed section contains two gas cylinders for oxygen, nitrogen and ethane. Gases coming from regulators pass through in-line filters molecular sieves, 5A are then introduced to the Mass Flow Controllers MFC , obtained from Bronkhorst.
On line samples reactor By-Pass from the feed gas mixture are directed to gas chromatograph for analysis. The micro-reactor overall length is mm with inside diameter of made of 8 mm stainless steel and surrounded by heater. Surrounding temperature can be controlled. The reactor temperatures are measured at three locations by means of thermocouple located in the catalyst bed. Reaction products as well as feed mixture are analyzed on-line using Varian system model CP RGA gas chromatograph.
Figures 2, of 1st group of catalyst Mo16V6. It was also obtained as shown in table1, lower C2H4 selectivity The decrease in C2H4 selectivity is accounted by an increase in CO2 selectivity and yield. Figure 3, of 2nd group of catalysts Mo16V6. Therefore drying temperature provides no significant effect on Ni-cat performance.
Figures 4, of 3rd group of catalysts Mo16V6. In conclusion, Ag-cats dried at higher temperatures did not improve performance. Figures 5 of 4th group of catalysts Mo16V6. Catalyst Composition rature, C Selec. Al-zeghayer , et al and unstable anions and cations that have been previously introduced, but is not desired in the final catalysts. Furthermore, the degrees of removal of un-wanted materials also affect the performance of the catalyst.
Removal of these un-wanted hydrocarbons depends on the procedure of the calcination such as temperature, duration and atmosphere . Increasing calcination temperature was found to: decreases i both C2H6 and O2 conversions particularly at lower reaction temperatures.
Therefore increasing the calcination temperature is not favorable as the results displays that increasing the calcinations temperature decrease the catalyst activity.
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This technique allows several 3-state chips to drive the same bus, with only one of them active at any given time. The serial data is input on the DS pin pin The 74HC is an 8-bit parallel-load shift register which has a serial output. It has complementary outputs, one of which can be tied to another 74HC to cascade them. This device is used for parallel to serial data conversion and has the following pinout:. As with the 74HC, this is a very common integrated circuit and you should have no trouble obtaining it at almost any electronics supplier.
In these experiments, we will be using it to drive some LEDs, which we will control using an Arduino. Note the addition of a decoupling capacitor, across the power supply, this is a good idea when working with TTL chips like the 74HC I used a uf capacitor but any value from 10uf upwards will work just fine.
Make sure that you observe the polarity of the capacitor. This is a convenient component to have when you need a lot of identical resistors. There are a lot of wires here so double-check your wiring. Repeat the test for all eight resistor-LED pairs.
Do this before you wire up the 74HC and the Arduino. Once it is all wired up you can move forward and write some code to make it all work. One way is to use the SPI bus, which would allow you to make use of existing libraries to simplify writing code.
This is the method we will employ to work with the 74HC shift register. Arduino provides a shiftOut function to simplify moving data on a serial connection. It can take a byte value and output it in a serial format in sync with a clock pulse on another pin. You can choose to output the data in two directions.
Our sketch is pretty simple. The shiftOut function takes care of sending our data to the shift register and of creating a clock signal. This sketch is just an adaptation of one that Arduino provides in their excellent lesson on using the 74HC with the Arduino. It uses the eight LEDs as the display for a binary counter.
We begin by assigning variable names to the pins connected to the 74HC All of these pins are then set up as outputs. We then move on to the Loop. We use a for-next loop to count from 0 to , incrementing by one. On each increment, we write the counter value out to the shift register. The result is that the LEDs display a binary count from 0 to You can experiment with the code and manipulate some values and observe the effect on the LEDs.
In some displays, this may be substituted with a colon. Both display types use the same pinout, so it is very important to know what type you have. When connected with the proper polarity it can be used to light the LED elements. The Common Cathode display is more common and is the type we will be using for our experiment. So we can use the exact same circuit to hook it up. Use the chart in the hookup diagram to connect the display pins to the dropping resistors.
Note that the display will have two COM pins, you only need to connect one. Once you have that all hooked up you can test it by running the previous sketch, which should test all the LED segments including the decimal point. But to actually display something coherent we will need a different sketch. Here is the sketch we will use to test out our 7-segment display.
We start again by defining our connections to the 74HC Then we create an array with 16 elements, each one representing the pattern for a character to display on the 7-segment LED. The elements are written in binary and it makes it simple to understand how they work. Within the binary byte, each bit represents one of the LED segments.
Once again in Setup, we set our connections as outputs and then move onto the Loop. Again we use a counter, only this time ist is between 0 and We will display these values as they are counted on the LED display in Hexadecimal format.
We step through the array one element at a time, using shiftOut to send the element data to the shift register. Load up the code and observe the display. For that job, we will use the 74HC We will use the 74HC shift register along with eight momentary-contact pushbutton switches. The shift register will take the 8 inputs from the switch and send them to the Arduino as serial data.
Once again Arduino has a dedicated function for receiving serial data. The shiftIn function shifts serial data in one byte at a time. As with its cousin the shiftOut function the shiftIn function also supplies a clock signal to synchronize the data transmission. The inputs of the 74HC need to be pulled down LOW to prevent false readings, so in addition to our eight pushbutton switches we will also need eight pulldown resistors.
I used 10k resistors, but any value from 4. Once again I used a uf decoupling capacitor, make sure you observe the polarity when connecting this. Once you have it all hooked up we can focus on the sketch we will be using to make this work. Our sketch is very simple, as all it does is read the status of the pushbuttons and display the results on the serial monitor.
The sketch starts out like all of our previous sketches, defining the four connections to the IC. In the Setup, we initialize the serial monitor and then set the connections up as required. In the Loop, we first write a pulse to the load pin, which will have it load the data from its parallel input into a buffer to be worked on.
We finish by taking the clock pin HIGH, signifying we are done. Load the sketch, open your serial monitor and observe the output. The data is all held HIGH on the output, the opposite of what is wired on the board. Pressing a pushbutton will cause it to read LOW, even though that is the opposite of what is really happening.
This is because we are using the complementary output from the 74HC Our data is inverted. Keep on reading! The example we just used has many practical applications, one of the obvious ones is as a keypad although there are better ways to make a large keypad. For a project that requires a lot of switches, it is a useful design technique. One great application of this circuit is to use it with DIP switches or jumpers, ones that are only occasionally set. You can use the 74NC to reduce the number of connections required to read an 8-position DIP switch, and just read it in the Setup routine so it is only read when the device is powered on or reset.
Of course, it would be a shame to have wired up all of those LEDs and switches without going the extra step to connect them together! If you built each of the demonstrations on its own solderless breadboard as I did then hooking both of them together is very simple. Leave the connections on the breadboard so that you can reconnect them to the other Arduino.
You can connect the 5-volt and Ground connections to the other breadboards power rails. When you are done try running the previous sketches on the Arduino, everything should still work. As our demo is essentially two demos fused together our sketch is pretty well the same thing.
The purpose of the sketch is to simply use the LEDs to display the status of the pushbuttons. Really boring, and a complete waste of a microcontroller and some shift registers, but as a demonstration, it works well.
We stare by once again defining pin connections to both integrated circuits. And in the Setup, we initialize the serial monitor and set the connections up as required. The Loop starts with the same routine we used earlier to read the pushbutton values from the 74HC Next, we use the same code we used earlier to write the data to the 74HC But we make one change to the date we send to the shift register.
Remember, our data from the switch is inverted. If we send it to the 74HC it will work, but the LEDs will all be on, except where we have pressed a pushbutton. The tilde squiggly symbol inverts the binary data, turning every zero into a one and vice versa. Exactly what we need to do. This matches how we receive it from the pushbuttons.
As we have eight switches we can select eight patterns. Then we have eight cases, one for each switch press. You could probably add more if you wanted to allow for pressing two buttons simultaneously, but eight was enough for me!
In each case section, we populate the datArray array with LED patterns, written in binary so they are easy to see. I used eight elements in the array to make it easier, but you can increase this to any number you like. Just change the number in the array definition and in the for-next loop that cycles through the array elements.
I set the delay between pattern changes to ms, but you can change that. Even better, try putting the delay as a variable in each case evaluation, so you can make the patterns run at different speeds. You could also make the speed variable by adding a potentiometer to one of the analog inputs and using it to set the delay time. Shift registers may be elementary building blocks that might seem out of place aside microcontrollers and other more capable chips, but they still can perform important functions in a modern design.
They can be very useful if you need to add extra inputs or outputs to your project, they are inexpensive and easy to use. Comments about this article are encouraged and appreciated. However, due to the large volume of comments that I receive, it may not be possible for me to answer you directly here on the website.
You are much more likely to get answers to technical questions by making a post on the DroneBot Workshop Forum. Your post will be seen not only by myself, but by a large group of tech enthusiasts who can quickly answer your question.
You may also add code samples, images and videos to your forum posts. Having said that, please feel free to leave constructive comments here. Please login or register. Did you miss your activation email? This topic This board Entire forum Google Bing. Print Search. Pages: [ 1 ] 2 Next All Go Down. Hi folks! I want to use it to simply divide a pulse signal. Here's the breadboard: It seemed an easy task at first, but I found out that it is not so Why do I get this from the outputs: When the datasheet says, that I should get this: It's messed up completly.
The Q A stage does invert?! The following stages Q B and Q C are not even close to a recognizable pattern. What could be wrong? Is it somehow necessary to "stabilize" the IC, that it can work correctly? I already found out, that a 0. Can someone give a hint? Thanks in advance! EDIT: You can jump right to this message , to see more pictures and a solution.
Hi, Your layout looks fine, but you may have a bad connection somewhere. The most likely reason though is because the other section of the counter has its inputs left in an undefined state. Try tying the two A side clocks and its reset to 0V, and it should eliminate any spurious interference from that side. Regards, Sarah. HC logic is very fast. Sub microsecond noise pulses, completely invisible at your ultra-slow timebase, can cause spurious clocking. It has happened to me. HC has a maximum input slew rate, so make sure your inputs are nice and fast edges.
EDIT: Yep, your clock pulse is coming from an opto-coupler, that will be a creating a slow positive edge. Try reducing your pullup resistor value for starters. I never leave unused 'HC logic inputs floating, like pin 1,2,4. I just shot a video on this question, editing now The following users thanked this post: LateLesley. The following users thanked this post: brabus , Darkwing.
You could use a "Johnson Counter" instead, if you just want to divide by That function was performed by a in astable mode, which was, in turn, triggered on by the output of the opto coupler which was used to isolate the local power supply from the telephone line power. When the device received a call, it would turn on the opto, starting the Ultimately, the whole shebang controlled an audio generator, which would perform a frequency response test of Broadcast programme lines on demand for staff at a remote site.
Wow, Dave, that's so amazing! I will follow up on this, presumably next week and I'll post results and my findings. For now, quick info: the Fall Time of my signal is ns in average [ns - ns]. So that alone seems problematic, very very slow. Will keep you updated! Thanks so far! Quote from: Darkwing on May 02, , pm. Quote from: Henry Petroski. The following users thanked this post: EEVblog. Brumby Supporter Posts: Country:. I'll add my voice to the "not a stupid question" chorus!
In fact, some of the most stupid questions are the ones that didn't get asked. Quote from: wilfred on May 03, , am. I was once told, "The only stupid question, is one you already know the answer to. So as you can see Q 1 Q 2 and Q 3 won't divide into perfect square waves, as there times when they are off for longer.
The same applies to Q 2 , it's off for 6 counts, but on for 4. So I would actually count out each step, and see if you are seeing intended behaviour for that chip. The rabbit hole goes deep And there is always more than one way to skin a cat Either a counter with a Schmitt input trigger input or When is DaveCadCon? I'll buy a ticket.
Nice to see FUNdament Friday's are back. Great video. Quote from: LateLesley on May 03, , am. MrAl Frequent Contributor Posts: Hello there, The output from an opto coupler has very slow rise and fall times unless it is made specifically for digital logic. As the output ramps up during the rise time, it eventually gets close to the threshold voltage of the logic gate input and then the always present noise can go above and below the threshold voltage several times before the ramp finally gets high enough to overcome the noise completely and then provide a stable logic state.
Before it gets past the noise it can clock a counter several times or just a few times just on that one rising or falling edge alone, and that will mean we will see a varying response from the counter chip which means we get garbage out. This is a very common problem even for circuits that dont use opto couplers.
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